The invention pertains to the field of custom circuits, and, more particularly, to the field of components and cells from which field reprogrammable logic circuits may be constructed and field programmable logic circuits themselves.
Logic designers have long had the need for custom logic circuits to implement their designs. In the 1970's, this need gave rise to programmable logic arrays, programmable array logic and programmable read only memory. Later in the decade, custom circuits were made by customizing the metal layer of integrated circuits which had standard cells formed in the layers below the metal layer. The customized metal layer interconnected the standard cells in a manner defined by the customer of the gate array manufacturer.
Gate arrays are only a good choice where the desired function to be performed by the gate array can be determined with certainty in advance. However, gate arrays are not a good choice where the desired function can change over time with changing requirements. This can happen when a circuit design is being evaluated and testing over time reveals the need for changes in the design. Another shortcoming of gate arrays was that they could not perform the function of packet encapsulation and delivery in network settings where packet construction was subject to a variety of different protocols and where packet headers change as the packets circulate, for example in token ring networks. This function has been done in software in the prior art, but increasing network speeds demands more speed which requires that this function be done in hardware.
Another application in which fixed gate arrays had shortcomings in where data flow paths change over time as a function of changes in the process that is being emulated by a particular circuit. Thus, a need arose for more flexibility in custom circuits such that the functions thereof can be changed.
Reprogrammable gate arrays, also called field programmable gate arrays or FPGAs, were developed in response to this need. However, these gate arrays were implemented in CMOS technology. Although CMOS has significant advantages such as low power, high circuit density, good reliability and low cost, CMOS is not fast enough for very high speed custom circuits needed in applications such as supercomputers, communication systems, high speed workstations, networks, automatic test equipment, parallel processor interconnects and design emulation systems. In very fast applications such as these, having any MOS device in the signal path seriously impedes the switching speed and impairs the performance of the machine. This is because the resistivity of CMOS and MOS devices is too high, and this coupled with the junction capacitances and other capacitances intrinsic to MOS devices causes delays.
Typical prior art field programmable gate arrays use passive programmable links to couple signals between standard cells of the gate array. Typically, a matrix of programmable connections make connections on the chip between various standard cells thereby defining the functionality of the chip. Prior art FPGAs made by Xilinx, Altera and Actel used passive devices which are programmed to make the connections between ports on the various standard cells to be coupled together. These passive connections defined a crossbar switch wherein any line could be connected to any other line through the passive programmable connectors to connect the standard cells together in the desired manner. Because these connections were made through these passive, programmable connectors, the high speed data propagating between standard cells was subjected to the parasitic series resistance and shunt capacitance of the passive connectors. These parasitic components formed RC low pass filters, which, because they were coupled to the high speed signal paths, slowed down the operation of the FPGA. Specifically, the RC low pass filters caused loss to the substrate of high frequency components in the Fourier spectrum of the high speed data. This loss caused sharp edges in the high speed data signals to be rounded and slowed pulse rise times thereby slowing the overall operation of the circuit.
All passive connections suffer this same infirmity because they are not able to replace any energy lost in the parasitics.
Accordingly, the need has arisen for a much faster technology that can be substituted for field programmable gate array circuits in extremely high speed applications using active links to couple different circuit elements together in a programmable fashion.